Meta Moves Iris AI Chip Into Production in September

Meta is about to become one of the largest manufacturers of custom 2-nanometre AI silicon, and it's doing it with a chip most of the industry has not been tracking closely.

An internal memo reviewed by Reuters shows that Meta plans to begin manufacturing its "Iris" chip - part of the company's Meta Training and Inference Accelerator (MTIA) program - this September. Testing cleared in roughly six weeks with no significant problems. Broadcom is the design partner; TSMC handles fabrication on a 2nm process node. The stated goal is direct: roughly double Meta's computing capacity while reducing what it spends on NVIDIA and AMD silicon.

TL;DR

Meta's "Iris" chip enters production in September 2026, per a Reuters-obtained internal memo
Manufactured by TSMC on a 2nm process, co-designed with Broadcom
Testing completed in 6 weeks with no major issues
Meta targets 7 GW compute capacity in 2026, 14 GW by 2027
Iris adds to NVIDIA/AMD buys for now - training frontier models still needs GPUs

Inside the Iris Chip

The Process Node: TSMC 2nm

Iris is one of a handful of custom AI accelerators to reach 2nm fabrication. TSMC's N2 process - which began quiet volume production late last year - delivers a 10-15% performance gain at identical power versus 3nm, and a 25-30% power reduction at the same performance level. For Meta's inference-heavy workloads, where efficiency at scale compounds into real cost differences, that node jump matters more than the raw FLOP count.

The 2nm slot isn't easy to get. Apple has booked more than half of TSMC's initial N2 capacity. Meta securing a meaningful allocation - for a chip that entered testing only six weeks before production - reflects how seriously TSMC is treating hyperscaler custom silicon customers.

The Broadcom Design Partnership

Meta formalized its Broadcom chip partnership in April 2026 in a deal that spans multiple MTIA generations through 2029 and commits to deploying over one gigawatt of computing capacity as an opening installment in a multi-gigawatt buildout. Broadcom brings packaging expertise and co-design experience from working with Google on TPUs; Meta brings workload data no outside vendor has.

The 2029 runway matters. It tells the industry that Meta isn't treating custom silicon as an experiment - it's treating it as a multi-year infrastructure commitment, the same way Google did with TPUs and Amazon did with Trainium and Inferentia.

Which MTIA Generation Is Iris?

Meta unveiled its four-generation MTIA roadmap in March 2026: MTIA 300 (in production for ranking and recommendations training), MTIA 400 (deploying now), MTIA 450 (scheduled for mass deployment early 2027), and MTIA 500 (2027). Based on the September production start and early-2027 mass deployment timeline, Iris is almost certainly MTIA 450 entering initial manufacturing ahead of broad rollout. Reuters did not specify the exact generation by number.

Meta MTIA chip family - official visual from Meta's custom silicon announcement Meta's four-generation MTIA chip family, unveiled in March 2026. Source: about.fb.com

MTIA 450 doubles the HBM bandwidth of MTIA 400 (18.4 TB/s versus 9.2 TB/s) and introduces custom low-precision data types optimized for GenAI inference. The jump in memory bandwidth - not raw compute - is the design priority. Meta's own engineers have said HBM bandwidth is the single most important factor for GenAI inference performance, which is why MTIA 450 trades TDP headroom for bandwidth density.

Chip	Status	HBM Bandwidth	HBM Capacity	FLOPs
MTIA 300	Production	6.1 TB/s	216 GB	1.2 PFLOPs (FP8)
MTIA 400	Deploying	9.2 TB/s	288 GB	6 PFLOPs (MX8)
MTIA 450 (Iris)	Sept 2026	18.4 TB/s	288 GB	21 PFLOPs (MX4)
MTIA 500	2027	27.6 TB/s	384-512 GB	30 PFLOPs (MX4)

The Production Timeline

The six-week testing window is unusually short for a new chip tape-out. Industry standard for first-silicon validation is three to six months; finding nothing major in six weeks either means the design was exceptionally conservative or the simulation-to-silicon fidelity at TSMC's 2nm node has improved significantly. The memo doesn't elaborate on methodology.

What matters practically is the September production date. That gives Meta roughly three months of ramp volume before year-end, enough to begin deploying into data centers in meaningful quantities before the 2027 capex cycle locks in.

The internal note cited by Reuters framed the motivation in unusually direct terms: "Adopting the latest GPUs at Meta's scale has been a heavy lift, and it has cost us time."

The Infrastructure Play

Meta and Broadcom partnership announcement for custom AI silicon Meta and Broadcom signed a multi-year chip co-development agreement in April 2026. Source: about.fb.com

Meta's computing ambitions have gotten larger with each public update. The current target is 7 gigawatts of capacity in 2026, scaling to 14 gigawatts by 2027. Capital expenditure guidance sits at $125-145 billion for 2026, with the majority directed at data centers and custom silicon.

Iris isn't a standalone purchase. Meta has also extended supply agreements with Samsung (memory chips), Sandisk (flash storage), and Sumitomo Electric (fiber-optic equipment) as part of the broader infrastructure buildout. The MTIA chips slot into existing rack infrastructure without modification - Meta designed the modularity in specifically to accelerate time-to-production.

This is the same strategy that made Meta's multi-billion dollar deals with NVIDIA and AMD's 6 GW compute agreement compatible with custom silicon: buy third-party GPUs for training, use MTIA for the inference workloads where cost-per-token matters most.

Server racks inside a large-scale AI data center Meta is building toward 14 GW of compute capacity by 2027, with custom silicon handling an increasing share of inference workloads. Source: unsplash.com

Where It Falls Short

The honest read on Iris is that it solves one class of problem while leaving the harder one to NVIDIA. Meta's own memo acknowledges Iris "will supplement rather than replace" GPU purchases. MTIA covers ranking, recommendations, and GenAI inference - workloads where the request profile is predictable and inference efficiency is the dominant cost driver. Pre-training frontier-scale models is a different computational regime completely: it needs the interconnect bandwidth, NVLink-style topology, and software ecosystem maturity that NVIDIA has spent a decade building.

MTIA 450 also has no public third-party benchmark data yet. The claim that MTIA 400 delivers "high performance competitive with leading commercial products" came from Meta's own March blog post. Independent validation is still missing - and until a chip is in production at scale, those comparisons are easier to make than to verify.

Finally, 2nm capacity is constrained globally. TSMC's initial N2 production is heavily allocated; Meta is competing for wafers with Apple, AMD, and others. A September production start doesn't automatically mean volume at scale by Q4.

Meta has spent three years building toward custom silicon credibility. The March MTIA roadmap established the architecture; the Broadcom partnership established the design pipeline; the September production date establishes that this is no longer a roadmap - it is a manufacturing program. Whether Iris can actually make a difference against a $145 billion capex commitment will show up in 2027 deployment numbers, when mass production scales and the real cost-per-token data arrives.

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